Semiconductor package including stacked chips

ABSTRACT

Semiconductor packages are disclosed. An exemplary package includes horizontal leads each having a first side and an opposite second side. The second side includes a recessed horizontal surface. Two stacked semiconductor chips are within the package and are electrically interconnected in a flip chip style. One chip extends over the first side of the leads and is electrically connected thereto. The chips are encapsulated in a package body formed of an encapsulating material. The recessed horizontal surface of the leads is covered by the encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal. A surface of one or both chips may be exposed. The stack of chips may be supported on the first side of the leads or on a chip mounting plate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor packagecontaining at least two stacked semiconductor chips.

[0003] 2. Description of the Related Art

[0004] Conventionally, a stack-type semiconductor package includes aplurality of semiconductor chips that are vertically stacked one on topof the other on a leadframe substrate or a printed circuit boardsubstrate. The stacked semiconductor chips are electrically connected toeach other and to the substrate. Since the package contains a pluralityof semiconductor chips, a high degree of functionality is accomplished.

[0005] A conventional stack-type semiconductor package 100 isillustrated in FIG. 1. Package 100 of FIG. 1 includes a printed circuitboard 1 as a substrate. First circuit patterns, each including a bondfinger 5, are formed on an upper surface of a core resin layer 3 ofprinted circuit board 1. Second circuit patterns, each including a land7, are formed on an opposite lower surface of resin layer 3. The firstand second circuit patterns are electrically connected with each otherthrough conductive via-holes 9 that extend through resin layer 3. Acover coat 11 formed of an insulative resin covers the upper and lowercircuit patterns, except for the bond fingers 5 and lands 7,respectively.

[0006] A first semiconductor chip 15 is bonded to a center portion of anupper surface of the printed circuit board 1 by adhesive 16. A smallersecond semiconductor chip 17 is bonded to an upper surface of the firstsemiconductor chip 15 by adhesive 16.

[0007] Input and output pads 13 of the first and second semiconductorchips 15 and 17 are each connected to a respective one of the bondfingers 5 of printed circuit board 1 by conductive wires 8. A pluralityof conductive balls 20 are each fused to a respective one of the lands 7that are formed on the lower surface of printed circuit board 1.

[0008] The first semiconductor chip 15, second semiconductor chip 17,and conductive wires 8 are encapsulated in a package body 18 that isformed using an encapsulating material that is molded onto the uppersurface of printed circuit board 1.

[0009] The conventional stack-type semiconductor package 100 describedabove has cost disadvantages because it includes a relatively costlyprinted circuit board. Moreover, when package 100 is mounted on amotherboard, package 100 has a substantial mounting height above themounting surface of the motherboard due to the combined heights of thestack of chips, the printed circuit board, the wire loops, and theconductive balls. Furthermore, because the semiconductor chips are fullyenclosed by the printed circuit board and the body of hardenedencapsulating material, heat generated by the semiconductor chips cannotbe easily released to the outside.

SUMMARY OF THE INVENTION

[0010] Various embodiments of leadframe-based semiconductor packages fora pair of stacked semiconductor chips are disclosed. An exemplarypackage includes a plurality of horizontal metal leads. Each lead has afirst side, an opposite second side, and an inner end. The second sideof each lead includes at least one recessed horizontal surface. Theinner ends of the leads face and thereby collectively define a chipplacement region wherein the stack of chips is located. The chips areelectrically connected to each other in a flip chip style. At least oneof the chips extends over the first side of the leads and iselectrically connected thereto by bond wires or other conductors such asreflowed metal balls or anisotropic conductive films. The stack of chipsis encapsulated in a body of a hardened encapsulating material. Therecessed horizontal surface of each of the leads is covered by theencapsulating material, and at least a portion of the second side ofeach of the leads is exposed as an external connector in a horizontalplane of a first exterior surface of the package body. A surface of oneor both of the chips may be exposed at the exterior of the package bodyto facilitate heat transfer. The stack of chips may be mounted on thefirst side of the leads or on a chip mounting plate located in the chipplacement region.

[0011] The disclosed packages provide numerous advantages over theconventional package disclosed above, including a lesser package heightabove a mounting surface and superior heat dissipation capabilities. Inaddition, by using a leadframe rather than an internal printed circuitboard substrate, the cost of the package is reduced.

[0012] These and other features and aspects of the present inventionwill be better understood in view of the following detailed descriptionof the exemplary embodiments and the drawings thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a cross-sectional side view illustrating a conventionalsemiconductor package.

[0014]FIGS. 2A and 2B are cross-sectional side views illustratingsemiconductor packages in accordance with a first embodiment of thepresent invention.

[0015]FIGS. 3A and 3B are cross-sectional side views illustratingsemiconductor packages in accordance with a second embodiment of thepresent invention.

[0016]FIGS. 4A and 4B are cross-sectional side views illustratingsemiconductor packages in accordance with a third embodiment of thepresent invention.

[0017]FIGS. 5A and 5B are cross-sectional side views illustratingsemiconductor packages in accordance with a fourth embodiment of thepresent invention.

[0018] Wherever possible, the same reference numerals are usedthroughout the drawings and the description of the exemplary embodimentsto refer to the same or like parts.

DETAILED DESCRIPTION

[0019]FIGS. 2A and 2B are cross-sectional side views illustratingalternative semiconductor packages 101 and 102, respectively, inaccordance with a first embodiment of the present invention. Packages101 and 102 include a first semiconductor chip 2 that is stacked with asecond semiconductor chip 4. Chips 2 and 4 respectively include a firstsurface 2 a or 4 a having bond pads 13 formed thereon, and an oppositesecond surface 2 b or 4 b. Second semiconductor chip 4 is mounted overfirst semiconductor chip 2 so that first surface 4 a and the bond pads13 thereon superimpose first surface 2 a and the bond pads 13,respectively, of first semiconductor chip 2. As shown, surfaces 4 a, 4 bof second semiconductor chip 4 are larger in area than the correspondingsurfaces 2 a, 2 b of first semiconductor chip 2, such that a peripheralportion of second semiconductor chip 4 overhangs the peripheral sides 2c of first semiconductor chip 2. In this embodiment, first surface 4 aof second semiconductor chip 4 includes bond pads 13 that are locatedboth on the central portion of first surface 4 a that superimposes firstsurface 2 a of first semiconductor chip 2 and on the peripheral portionof first surface 4 a that overhangs peripheral sides 2 c of firstsemiconductor chip 2.

[0020] A plurality of horizontal metal leads 12 are located at thebottom exterior first surface 18 a of package body 18. Leads 12 arecollectively provided fully around first semiconductor chip 2, as in aquad package, and below first surface 4 a of second semiconductor chip4. (Alternatively, leads 14 may be provided adjacent to two sides 2 c offirst chip 2, as in a dual package). The inner ends 12 b of the leads 12face the peripheral sides 2 c of first semiconductor chip 2 and therebycollectively define a central area within which first semiconductor chip2 is located. By having semiconductor 2 and 4 stacked in this way, thatis, with first semiconductor chip 2 positioned at a central arealaterally between the inner ends 12 b of leads 12, the thickness ofsemiconductor packages 101 and 102 can be remarkably reduced despitehaving two chips stacked therein.

[0021] As shown in FIG. 2A, each lead 12 has an inner end 12 b thatfaces first semiconductor chip 2 and an opposite outer end 12 c that isexposed outside of package body 18. An inner portion of the lower side12 e of each lead 12 beginning at inner end 12 b is partially etchedthrough in a vertical direction, so as to form a horizontal undercutregion, denoted as horizontal recessed surface 12 a, of a predetermineddepth. A remaining portion of the lower side 12 e of each lead 12 thatis laterally between recessed surface 12 a and the outer end 12 c of thelead 12 defines a land 14. Lands 14 are exposed at lower first surface18 a of package body 18 and are the input/output terminals of package101. During the encapsulation step, the encapsulating material thatforms package body 18 fills in under recessed surface 12 a, therebypreventing the lead 12 from being pulled vertically from body 18.

[0022] Alternatively, the lower side 12 e of each lead 12 may include aplurality of undercut regions each formed by partially etching throughthe thickness of lead 12. For example, as shown in FIG. 2B, each lead 12includes two horizontal recessed surfaces 12 a at the lower side of thelead. By having the two partial etched parts 12 a, two lands 14 aredefined on the lower surface of each lead 12. When viewed from below,the lands 14 of the plurality of leads 12 are exposed and collectivelyarrayed at a lower horizontal first surface 18 a of package body 18 insuch a way as to produce rows and columns of lands 14 at first surface18 a.

[0023] The input and output pads 13 of first semiconductor chip 2 eachsuperimpose one of a centrally located subset of the input and outputpads 13 of second semiconductor chip 4 and are electrically connectedthereto in a flip chip style by conductive connection means 6. Theremaining peripheral input and output pads 13 of second semiconductorchip 4 each superimpose the upper first side 12 d of a respective one ofthe leads 12, and are electrically connected thereto in a flip chipstyle by conductive connection means 6.

[0024] Metal balls, such as gold balls or solder balls, can be used asconnection means 6. Alternatively, instead of using metal balls, ananisotropic conductive film (ACF) can be used as connection means 6.

[0025] Each anisotropic conductive film comprises an amalgamation of aconventional bonding film and conductive metal grains. A thickness ofthe bonding film is about 50 μm, and a diameter of each conductive metalgrain is about 5 μm. A surface of the conductive metal grain is coatedwith a thin polymer layer. If heat or pressure is applied to apredetermined region of the anisotropic conductive film, the thinpolymer layers of the conductive metal grains in the predeterminedregion are melted so that adjacent metal grains become connected,thereby providing conductivity. The thin polymer layer of the remainingconductive metal grains, i.e., those not included in the predeterminedregion, are maintained in an insulated status. Therefore, a positionsetting operation between two component elements to be electricallyconnected can be implemented in an easy manner.

[0026] In a case where gold balls or solder balls (or other metal balls)are used as the conductive connection means 6, after the gold balls orsolder balls are fused to predetermined regions of the semiconductorchip or the leads, a reflow process must be performed after a positionsetting operation in order to make an electrical connection. On theother hand, where the anisotropic conductive films are used as theconductive connection means 6, after the anisotropic conductive filmsare applied over relatively wide areas on the semiconductor chip or theleads, and the semiconductor chip and the leads are properly positionedwith respect to each other, then the semiconductor chip and the leadscan be electrically connected with each other by simply exerting apressing force of a desired level. For example, if the anisotropicconductive films are applied over wide areas on the second semiconductorchip 4 or the upper first side 12 d of the leads 12, then by bringingthe second semiconductor chip 4 and the leads 12 into close contact witheach other, the input and output pads 13 of the second semiconductorchip 4 exert pressure onto predetermined regions of the anisotropicconductive films, whereby the peripheral input and output pads 13 of thesecond semiconductor chip 4 and the upper first first side 12 d of therespective leads 12 are electrically connected with each other.

[0027] Accordingly, while it is illustrated in the drawings that metalballs are used as the conductive connection means 6, practitionersshould understand that the metal balls can be replaced with anisotropicconductive films in all embodiments of the present invention. Using aflip chip style mounting for second semiconductor chip 4 on leads 12through a connection means 6 eliminates the need for conductive wires,as in FIG. 1, thereby eliminating the need for package body 18 to coverthe apex of the wire loops, and subsequently reducing the height of thesemiconductor packages 101 and 102.

[0028] Also, where metal balls are used as the conductive connectionmeans 6, insulating layers 22 of a predetermined thickness may be coatedon the upper first first side 12 d of each of the leads 12 around thesurface portions thereof where the leads 12 are connected with theperipheral input and output pads 13 of the second semiconductor chip 4.The insulating layers 22 each prevent the metal ball that is bonded fromoverflowing the desired bonding area, whereby shorts between adjacentballs, inferior connections between the second semiconductor chip 4 andthe leads 12, or the like, can be avoided. The insulating layer 22 onfirst first side 12 d of each lead 12 has an aperture through which themetal ball can be inserted to accurately locate the connection means 6to the appropriate area of upper first side 12 d of the lead 12 forbonding thereto.

[0029] While a variety of materials can be used to form the insulatinglayer 22, it is preferred that a solder mask, a cover coat or polyimidebe employed.

[0030] The first semiconductor chip 2, second semiconductor chip 4,conductive connection means 6 and leads 12 are encapsulated in a packagebody 18 formed from an insulative encapsulating material. Theencapsulation step is performed so that at least a portion of the lowerside 12 e of each of the leads 12, in particular, the land(s) 14, areexposed to the outside in the horizontal plane of lower first surface 18a of package body 18. Because the recessed surface 12 a of each lead 12is covered (i.e., underfilled) by the encapsulating material of packagebody 18, the lead 12 is prevented from disengaging from the package body18 in a horizontal or vertical direction and instead is maintained in arigidly secured status. Typically, encapsulation is performed by moldingand curing an insulative resin (e.g., epoxy) material. Alternatively, aliquid encapsulant may be used.

[0031] The exposed lands 14 at lower first surface 18 a of the packagebody 18 of semiconductor package 101 can be electrically connected to amotherboard using solder. Also, as can be readily seen from FIG. 2B,optional conductive balls 20, such as lead tin solder balls, can befused to the exposed lands 14, as in a ball grid array package, so thatthe semiconductor package 102 can be electrically connected to amotherboard.

[0032]FIGS. 3A and 3B are cross-sectional side views illustratingsemiconductor packages 103 and 104 in accordance with a secondembodiment of the present invention. Since semiconductor packagesaccording to this second embodiment of the present invention areconstructed in a similar manner to the semiconductor packages of thefirst embodiment discussed above, only differences existing therebetweenwill be described hereinbelow.

[0033] As shown in FIGS. 3A and 3B, the encapsulation step (typically amolding process) is performed so that inactive second surface 2 b offirst semiconductor chip 2 is exposed to the outside at a horizontallower first surface 18 a of package body 18. Moreover, inactive secondsurface 4 b of second semiconductor chip 4 is exposed in the horizontalplane of the horizontal upper second surface 18 b of the package body18. Accordingly, heat generated in the first semiconductor chip 2 can bereleased or dissipated into the air through the exposed second surface 2b, and heat generated in second semiconductor chip 4 can be released ordissipated into air through the exposed second surface 4 b and throughthe leads 12. As a consequence, the heat dissipation capability ofsemiconductor package 103, 104 is drastically improved by comparison tothe package of FIG. 1.

[0034] Moreover, in the case of semiconductor package 104 of FIG. 3B, alayer of a conductive paste (not shown), for example, a solder paste,may be formed on the exposed second surface 2 b of first semiconductorchip 2. The layer of conductive paste has a vertical thickness similarto that of the conductive balls 20. During a process of mounting such asemiconductor package 104 on a motherboard, the conductive paste can beconnected to a heat sink or ground terminal of the motherboard, wherebyheat generated in the first semiconductor chip 2 can be easilytransferred to the motherboard and from there into air.

[0035]FIGS. 4A and 4B are cross-sectional side views illustratingsemiconductor packages 105 and 106 in accordance with a third embodimentof the present invention. Again, our discussion will focus on thedifferences between these packages and those discussed above, ratherthan again describing the many similar features.

[0036] Packages 105, 106 include a first semiconductor chip 2 having anactive first surface 2 a on which a plurality of input and output pads13 are formed, and a second semiconductor chip 4 having an active firstsurface 4 a on which a plurality of input and output pads 13 are formed.First semiconductor chip 2 is larger than second semiconductor chip 4,and includes input and output pads 13 both at central and peripheralportions of first surface 2 a. Second semiconductor chip 4 is mounted ina flip chip style on first semiconductor chip 2 so that the firstsurface 4 a of semiconductor chip 4, including the input/output pads 13thereon, superimposes a central portion of first surface 2 a of firstsemiconductor chip 2. The input/output pads 13 of second semiconductorchip 4 are each superimposed and are electrically connected to arespective one of the central input/output pads 13 located on thecentral portion of first surface 2 a of first semiconductor chip 2.

[0037] A metal die pad, called chip mounting plate 10 herein, isprovided at a central region of package 105, 106. Chip mounting plate 10has a rectangular shape perimeter, and a first side 10 b to whichinactive second surface 2 b of first semiconductor chip 2 is bonded withan adhesive 16, which may be a layer of an adhesive resin (e.g., epoxy),an adhesive film, or a double sided tape. An opposite second side 10 cof chip mounting plate 10 includes a central surface 10 d that isexposed in the horizontal plane of horizontal exterior first surface 18a of package body 18 inside of lands 14 of leads 12. A horizontalundercut region, denoted as recessed surface 10 a, is formed bypartially etching through chip mounting plate 10 from second side 10 ctoward first side 10 b. Recessed surface 10 a surrounds lower centralsurface 10 d. Since horizontal recessed surface 10 a is recessed fromand fully surrounds central surface 10 d, chip mounting plate 10 has alip at first surface 10 a that fully surrounds chip mounting plate 10.

[0038] A plurality of horizontal leads 12 are provided around two or allfour sides of chip mounting plate 10. The leads 12 are in the samehorizontal plane as chip mounting plate 10, with a predeterminedseparation between an inner end 12 b of each lead and the periphery ofchip mounting plate 10. Inner end 12 b faces chip mounting plate 10.

[0039] As shown in FIG. 4A, an inner portion of the lower side 12 e ofeach lead 12, beginning at inner end 12 b of the lead 12, has ahorizontal recessed surface 12 a of a predetermined depth. The remainingportion of the lower side 12 e of each lead 12, i.e., the portion fromrecessed surface 12 a outward to exposed outer end 12 c of the lead 12,defines a land 14 exposed in the horizontal plane of horizontal firstsurface 18 a of body 18.

[0040] In FIG. 4B, each lead 12 is undercut at two locations of thelower side of the lead 12 so as to have two horizontal recessed surfaces12 a. The two recessed surfaces 12 a define two lands 14 at the lowerside of each lead 12. Lands 14 are exposed at horizontal first surface18 a of body 18 and function as input/output terminals of the package.Optionally, conductive balls 20 may be fused to lands 14. When viewedfrom below, the lands 14 of the plurality of leads 12 are arrayed insuch a way as to produce rows and columns at lower first surface 18 a ofpackage body 18.

[0041] Referring to FIGS. 4A and 4B, the first semiconductor chip 2extends over the upper first side 12 d of the leads 12. In other words,a peripheral portion of second surface 2 b of first semiconductor chip 2overhangs the sides of chip mounting plate 12 and superimposes the upperfirst s side 12 d of leads 12. This peripheral portion of second surface26 may be bonded to the upper first side 12 d of each of the leads 12 bya layer of insulative adhesive 16, as in FIG. 4B. Accordingly, leads 12support the overhanging periphery of first semiconductor chip 2, whichcan prevent first semiconductor chip 2 from being tilted during a wirebonding process.

[0042] During the wire bonding process, the peripheral input and outputpads 13 on first surface 2 a of first semiconductor chip 2 that are notsuperimposed by second semiconductor chip 4 are each electronicallyconnected to the upper first side 12 d of respective leads 12 byconductive wires 8, which may be gold wires or aluminum wires. The upperfirst side 12 d of the leads 12 can be plated with gold (Au), silver(Ag), palladium (Pd) or the like so as to provide a stronger connectionwith the conductive wires 8. The centrally-located input and output pads13 of the first semiconductor chip 2, i.e., those superimposed by theinput/output pads 13 of second semiconductor chip 4, are electricallyconnected thereto by conductive connection means 6.

[0043] Here, as described above, the conductive connection means 6 canbe selected from a group consisting of metal balls (e.g., gold or solderballs) and anisotropic conductive films, among other possibilities.

[0044] The first semiconductor chip 2, second semiconductor chip 4, chipmounting plate 10, leads 12, conductive wires 8 and conductiveconnection means 6 are encapsulated (e.g., by molding) using aninsulative encapsulating material, in a manner such that the centralsurface 10 d of the lower second side 10 c chip mounting plate 10 andthe lands 14 of each of the leads 12 are exposed to the outside in thehorizontal plane of first surface 18 a of package body 18, whilerecessed surface 12 a is covered by the encapusulating material.Accordingly, heat generated in the first semiconductor chip 2 and thesecond semiconductor chip 4 is dissipated to the outside through thechip mounting plate 10 and leads 12. Accordingly, the heat dissipationcapability of the entire semiconductor packages 105 and 106 is markedlyimproved by comparison to the conventional package of FIG. 1.

[0045] Semiconductor package 105 of FIG. 4A can be electricallyconnected to a motherboard by bonding solder between each land 14 and aterminal of the motherboard. Semiconductor package 106 of FIG. 4B can beelectrically connected to a motherboard by fusing the conductive ball 20previously formed on land 14 of each lead 12 to the terminals of themotherboard. In addition, a conductive layer, such as a solder paste,having a bond line thickness similar to that of the conductive balls 20can be formed on the exposed lower central surface 10 d of the chipmounting plate 10 of the semiconductor package 106 of FIG. 4B. Asdescribed above, such a conductive layer may later be connected to aheat sink or ground terminal of the motherboard, so as to transfer heatgenerated in the first and second semiconductor chips 2 and 4 throughchip mounting plate 10 to the motherboard.

[0046]FIGS. 5A and 5B are cross-sectional side views illustratingsemiconductor packages 107 and 108 in accordance with a fourthembodiment of the present invention. Since semiconductor packagesaccording to this fourth embodiment of the present invention areconstructed in a similar manner to the semiconductor packages accordingto the third embodiment of the present invention, only differencesexisting therebetween will be described hereinbelow.

[0047] As shown in FIGS. 5A and 5B, an upper, inactive second surface 4b of second semiconductor chip 4 is exposed externally in the horizontalplane of horizontal second surface 18 b of package body 18, similar toFIGS. 3A and 3B. Accordingly, heat generated in first semiconductor chip2 and second semiconductor chip 4 is released into air through the lowerfirst surface 10 c of chip mounting plate 10 and through the exposedsecond surface 4 b of second semiconductor chip 4. Accordingly, the heatreleasability of the entire semiconductor package 107, 108 is improved.

[0048] Further, as in the packages of FIGS. 2A and 2B, semiconductorpackages 107 and 108 may have a conductive connection means 6 selectedfrom a group consisting of metal balls (e.g., gold or solder balls) andanisotropic conductive films. Also, in the case of the semiconductorpackage 108 in FIG. 5B, a layer conductive of a conductive paste can befurther formed on the exposed lower central surface 10 d of the chipmounting plate 10.

[0049] The semiconductor packages described above feature an inexpensiveleadframe in place of the costly printed circuit board of FIG. 1,thereby reducing a manufacturing cost of the semiconductor package.Further, the leadframe is at the bottom of the package body, whichreduces package height.

[0050] Also, in some of the embodiments where a lower semiconductor chipis positioned in an empty central area defined between the inward facingends of the leads, which are separated from each other by apredetermined distance, the thickness of the entire semiconductorpackage is decreased.

[0051] Moreover, the use of flip-chip style conductive connection meansfor electrically interconnecting the two stacked chips to each otherand, in some cases, for electrically connecting the larger one of thechips to the leads, eliminates the need for one or both sets of bondwires (compare FIG. 1), thereby reducing the thickness of thesemiconductor package still further.

[0052] Further, in embodiments where the inactive surface of one or bothof the stacked semiconductor chips are exposed out of the package body,or where the inactive surface of the upper one of the two stackedsemiconductor chips and a surface of a chip mounting plate are exposedout of the package body, the heat releasability of the entiresemiconductor package is improved by the comparison to the package ofFIG. 1.

[0053] Furthermore, in the case where a layer of a conductive paste isformed on either an exposed lower inactive surface the lower chip of thestack or on the exposed lower surface of a chip mounting plate, theconductive paste layer can be thermally and/or connected to amotherboard to which the package is mounted, thereby providing anadditional heat dissipation path ground voltage source for the mountedpackage.

[0054] In addition, when the semiconductor chips and the leads areelectronically interconnected using conductive metal balls as theconductive connection means, an insulating layer of a predeterminedthickness and having a central aperture can be coated on the uppersurface of the respective leads. The metal balls (e.g., gold balls orsolder balls) can each be fused to the upper surface of a respective oneof the leads through the aperture in the insulating layer, therebyensuring that an accurate conductive connection between the chip andlead is implemented in an easy and reliable manner.

[0055] In the drawings and specification, although specific terms may beemployed in describing the exemplary embodiments, they are used in ageneric and descriptive sense only and not for purposes of limitation.The scope of the invention is set forth in the following claims.

What is claimed is:
 1. A semiconductor package comprising: a plurality of horizontal metal leads, each lead having a first side, an opposite second side, and an inner end, wherein the inner ends of the leads each face a central region in a horizontal plane of the leads; a first semiconductor chip having input/output pads, said first chip located in the central region; a second semiconductor chip having central input/output pads and peripheral input/output pads, wherein each of the central input/output pads superimposes and is electrically connected to a respective one of the input/output pads of the first semiconductor chip, and each of the peripheral input/output pads superimposes and is electrically connected to the first side of a respective one of the leads; and a package body formed of a hardened encapsulating material, wherein the first and second semiconductor chips are encapsulated in the package body, and at least a portion of the second side of each of the leads is exposed at a horizontal first exterior surface of the package body.
 2. The semiconductor package of claim 1, wherein the second side of each lead includes at least one recessed horizontal surface covered by said encapsulating material.
 3. The semiconductor package of claim 1, wherein the second side of each lead includes a recessed horizontal surface at the inner end of the lead, said recessed horizontal surface being covered by said encapsulating material.
 4. The semiconductor package of claim 1, wherein the second sides of the leads exposed at said first exterior surface collectively form rows and columns.
 5. The semiconductor package of claim 1, wherein the second side of each lead includes at least one recessed horizontal surface covered by said encapsulating material and at least two surfaces exposed at the first exterior surface of the package.
 6. The semiconductor package of claim 1, wherein a surface of the first semiconductor chip is exposed at the first exterior surface of the package body, and a surface of the second semiconductor chip is exposed at an opposite second exterior surface of the package body.
 7. The semiconductor package of claim 1, wherein a surface of at least one of the first and second semiconductor chips is exposed at an exterior surface of the package body.
 8. The semiconductor package of claim 1, wherein the input/output pads of the first chip are each electrically connected to the central input/output pads of the second chip, and the peripheral input/output pads of the second chip are each electrically connected to the first side of the lead, by a reflowed metal ball or an anisotropic conductive film.
 9. The semiconductor package of claim 1, wherein a first surface of the first semiconductor chip is exposed at the first exterior surface of the package body, said first surface being covered by a layer of a conductive paste, and each exposed portion of the second side of each lead has a conductive ball thereon.
 10. The semiconductor package of claim 1, wherein each exposed portion of the second side of each lead has a conductive ball thereon.
 11. The semiconductor package of claim 1, further comprising an insulative layer on the first side of each lead, wherein the peripheral input/output pads of the second semiconductor chip are electrically connected to the first side of the lead through said insulative layer.
 12. A semiconductor package comprising: a chip mounting plate having a first side and an opposite second side; a plurality of horizontal metal leads, each lead having a first side, an opposite second side, and an inner end facing the chip mounting plate; a first semiconductor chip having a first surface and an opposite second surface, wherein the first surface includes central input/output pads and peripheral input/output pads and the second surface is mounted on the first side of the chip mounting plate; a second semiconductor chip having a first surface with input/output pads thereon, wherein each of the input/output pads of the second semiconductor chip superimposes and is electrically connected to a respective one of the central input/output pads of the first semiconductor chip; a plurality of metal wires each electrically connected between the first side of a respective one of the leads and a respective one of the peripheral bond pads of the first semiconductor chip; and a package body formed of a hardened encapsulating material, wherein the first and second semiconductor chips are encapsulated in the package body, and at least a portion of the second side of each of the leads is exposed at a horizontal first exterior surface of the package body.
 13. The semiconductor package of claim 12, wherein the second surface of the first semiconductor chip superimposes the first side of the leads.
 14. The semiconductor package of claim 12, wherein the second side of each lead includes at least one recessed horizontal surface covered by said encapsulating material.
 15. The semiconductor package of claim 12, wherein the second side of each lead includes a recessed horizontal surface at the inner end of the lead, said recessed horizontal surface being covered by said encapsulating material.
 16. The semiconductor package of claim 12, wherein the second sides of the leads exposed at said first exterior surface collectively form rows and columns.
 17. The semiconductor package of claim 12, wherein the second side of each lead includes at least one recessed horizontal surface covered by said encapsulating material and at least two surfaces exposed at the first exterior surface of the package.
 18. The semiconductor package of claim 12, wherein a central portion of the second side of the chip mounting plate is exposed at the first exterior surface of the package body, and a surface of the second semiconductor chip is exposed at an opposite second exterior surface of the package body.
 19. The semiconductor package of claim 12, wherein a surface of the second semiconductor chip is exposed at a second exterior surface of the package body.
 20. The semiconductor package of claim 12, wherein the second surface of the first semiconductor chip is supported on the first side of the leads by an insulative layer, said insulative layer being covered by said encapsulating material.
 21. The semiconductor package of claim 12, wherein the central input/output pads of the first chip are each electrically connected to the input/output pads of the second chip by a reflowed metal ball or an anisotropic conductive film.
 22. The semiconductor package of claim 12, wherein a portion of the second side of the chip mounting plate is exposed at the first exterior surface of the package body, said portion being covered by a layer of a conductive paste, and the exposed portion of the second side of each lead has a conductive ball thereon.
 23. The semiconductor package of claim 12, wherein each exposed portion of the second side of each lead has a conductive ball thereon.
 24. The semiconductor package of claim 12, wherein the second side the chip mounting plate includes a central surface and a recessed horizontal surface surrounding the central surface, and said recessed horizontal surface is covered by said encapsulating material.
 25. The semiconductor package of claim 12, wherein the second side the chip mounting plate includes a central surface exposed at the first exterior surface of the package body, and a recessed horizontal surface surrounding the central surface, and said recessed horizontal surface is covered by said encapsulating material.
 26. The semiconductor package of claim 25, wherein the second surface of the first semiconductor chip superimposes the first side of the leads.
 27. The semiconductor package of claim 25, wherein the second side of each lead includes at least one recessed horizontal surface covered by said encapsulating material.
 28. A semiconductor package comprising: a plurality of horizontal metal leads, each lead having a first side, an opposite second side, and an inner end wherein the second side of each lead includes at least one recessed horizontal surface and the inner ends of the leads face a central chip placement region; first and second semiconductor chips stacked in said chip placement region, each said chip having input/output pads, wherein at least some of the input/output pads of the first semiconductor chip face and are electrically connected to respective ones of the input/output pads of the second semiconductor chip by a first conductor, and other input/output pads of one of the first and second semiconductor chips are over the first side of the leads and are electrically connected to the first side of a respective ones of leads by a second conductor; and a package body formed of a hardened encapsulating material, wherein the first and second semiconductor chips and the conductors are encapsulated in the package body, the recessed horizontal surface of each of the leads is covered by the encapsulating material, and at least a portion of the second side of each of the leads is exposed at a horizontal first exterior surface of the package body.
 29. The semiconductor package of claim 28, further comprising a chip mounting plate in said chip placement region and having a first side and an opposite second side, wherein the first and second semiconductor chips are stacked on the first side of the mounting plate, and the second side the chip mounting plate includes a central surface exposed at the first exterior surface of the package body and a recessed horizontal surface surrounding the central surface, said recessed horizontal surface being covered by said encapsulating material.
 30. The semiconductor package of claim 28, wherein the input/output pads over the first side of the leads each face and are electrically connected to the first side of the lead.
 31. The semiconductor package of claim 28, wherein the first conductor is a reflowed metal ball or an anisotropic conductive film, and the second conductor is a metal wire.
 32. The semiconductor package of claim 28, wherein the first and second conductors are an anisotropic conductive film.
 33. The semiconductor package of claim 28, wherein one of the first and second semiconductor chips is in a horizontal plane with the leads in said chip placement region. 